1. Field of the Invention
The present invention relates to semiconductor memory, and more particularly to a device and method for eliminating early read problem in static memories.
2. Description of the Related Art
As technology scales, inter-die and intra-die variations in process parameters (e.g., channel length (L), width (W), threshold voltage (Vt), etc.) have become serious problems in circuit design. For example, the device-to-device (intra-die) variations in L, W or Vt between neighboring transistors in a static random access memory (SRAM) cell can significantly degrade not only in stability of the cell but in read and write delays. Thus, the timing of the read, write control signals play a crucial role in determining the functionality of SRAM.
The early read problem occurs when a wordline is turned on before write control signals. This takes place in a “fast cell condition”.
Referring to FIG. 1, a schematic diagram of an SRAM memory circuit 10 is shown along with a timing diagram to illustrate an early read condition. A cell 11 includes cross-coupled inverters that are written to and read from using bitlines 14a and 14b and a wordline 16. It is preferable to have bitlines 14a and 14b activated after the wordline. Bitlines 14 are activated in accordance with a write control signal 15 (e.g., active low) and a bit decode signal 17 (e.g., active low). When wordline signal 13 is activated (goes high), if the write control 15 and bit decode 17 signals are out of synch and arrive later than signal 13 as shown in FIG. 1, an early read before write condition 19 occurs on the left bitline 14a. This condition causes synchronization concerns and may result in the loss of data.